1. Field of Invention
The present invention relates to a method of forming a semiconductor device, and more generally to a method of forming a semiconductor device having a metal gate.
2. Description of Related Art
As the dimension of a semiconductor device is getting smaller, the dimension of the gate structure and therefore the thickness of the gate dielectric layer are reduced accordingly. The gate dielectric layer usually includes silicon oxide. A leakage current occurs when the SiO2 gate dielectric layer becomes thinner. To reduce the leakage current, one known method is to use a high dielectric constant (high-k) material instead of silicon oxide for forming the gate dielectric layer. However, under the condition of using a high-k material as a gate dielectric layer, the polysilicon gate may react with the high-k material to generate the so-called Fermi-level pinning, such that the threshold voltage is increased and the performance of the device is affected.
To avoid an increase in the threshold voltage caused by the reaction between the polysilicon gate and the high-k material, one known method is to use a metal layer as a gate. The conventional method for forming a metal gate is to deposit a silicon oxide layer to cover a dummy gate after the dummy gate is formed on a substrate. Thereafter, a portion of the silicon oxide layer is removed with a chemical polishing chemical (CMP) process to expose the dummy gate. Afterwards, the dummy gate is removed to form a gate trench in the silicon oxide layer. A metal gate is then formed in the gate trench. However, dummy gate residues are often observed after the dummy gate is removed. Such dummy gate residues are undesirable and may deteriorate the performance of the metal-gate device.